// **************************************************************
// COPYRIGHT(c)2021, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2021 
// Author       : MM 
// Email        : 
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
module frame_test_gen #(
     // parameter frame_mac_dst=48'h1000_0000_0001,
   	 // parameter frame_mac_src=48'h1000_0000_0002,
   	 parameter frame_length =16'h88b6
   	)
	(
    input  wire [47:0] frame_mac_dst  ,
    input  wire [47:0] frame_mac_src  ,
    
    input              clk            ,
    input              rst_n          ,
    input 	           frame_start    ,
    input              frame_rdy      ,
         
    output reg         pkt_test_sop   ,
    output reg         pkt_test_dvld  ,
    output reg         pkt_test_dsav  ,
    output reg [255:0] pkt_test_data  ,
    output reg         pkt_test_eop
	);  
reg [4:0]frame_cnt;
//配置frame_start有效且系统准备接受有效则开始发帧   10Gbps线速  每21个clk发一次  
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		frame_cnt <= 0;
	end
	else if(frame_cnt == 5'd21)begin
		frame_cnt <= 0 ;
	end 
	else if(frame_start && frame_rdy)begin
		frame_cnt <= frame_cnt + 1 ;
	end
end
//判别插入帧还是端口帧
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		pkt_test_dsav <= 0;
	end 
	else if((frame_cnt == 1)||(frame_cnt == 2))begin
		pkt_test_dsav <= 1'b1;
	end
	else begin
		pkt_test_dsav <= 0;
	end
end
//帧有效vld
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		pkt_test_dvld <= 0;
	end 
	else if((frame_cnt == 2)||(frame_cnt == 3))begin
		pkt_test_dvld <= 1'b1;
	end
	else begin
		pkt_test_dvld <= 0;
	end
end
//frame_cnt == 2  帧头
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		pkt_test_sop <= 0;
	end 
	else if(frame_cnt == 2)begin
		pkt_test_sop <= 1'b1;
	end
	else begin
		pkt_test_sop <= 0;
	end
end
//frame_cnt == 3  帧尾
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		pkt_test_eop <= 0;
	end 
	else if(frame_cnt == 3)begin
		pkt_test_eop <= 1'b1;
	end
	else begin
		pkt_test_eop <= 0;
	end
end
//64B帧  计数2/3发两次   
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		pkt_test_data <= 0;
	end 
	else if(frame_cnt == 2)begin
		pkt_test_data <= {frame_mac_dst,frame_mac_src,frame_length,144'b0};
	end
	else if(frame_cnt == 3)begin
		pkt_test_data <= 256'b1;
	end
	else begin
		pkt_test_data <= pkt_test_data;
	end
end

endmodule